Skip to content

[bugfix][risc-v]fix the PPN length error in GET_PPN(pte). #10020

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Feb 28, 2025

Conversation

GorrayLi
Copy link
Contributor

@GorrayLi GorrayLi commented Feb 22, 2025

拉取/合并请求描述:(PR description)

[

为什么提交这份PR (why to submit this PR)

libcpu\risc-v\common64\mmu.h中宏参数有误:

#define GET_PPN(pte)                                                           \
    (__PARTBIT(pte, PTE_PPN_SHIFT, PHYSICAL_ADDRESS_WIDTH_BITS - PTE_PPN_SHIFT))

其中第三个参数为PPN的bit位数,即44位,而PHYSICAL_ADDRESS_WIDTH_BITS为物理地址总位数即56,PTE_PPN_SHIFT为10(对应PTE的属性位数),56-10=46,显然不是44。
物理地址的组成为44bit PPN + 12bit page offset,因此这里正确的计算方式应该是,
PPN位数=物理地址总位数( PHYSICAL_ADDRESS_WIDTH_BITS(=56) ) - page offset位数( PAGE_OFFSET_BIT(=12) )= 44 bit。

你的解决方案是什么 (what is your solution)

将PTE_PPN_SHIFT修改为PAGE_OFFSET_BIT.

请提供验证的bsp和config (provide the config and bsp)

  • BSP:

  • .config:

  • action:

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

  • 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
  • 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality:

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

  • 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
  • 代码风格正确,包括缩进空格,命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
  • 没有垃圾代码,代码尽量精简,不包含#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up
  • 所有变更均有原因及合理的,并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
  • 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
  • 代码是高质量的 Code in this PR is of high quality
  • 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification
  • 如果是新增bsp, 已经添加ci检查到.github/workflows/bsp_buildings.yml 详细请参考链接BSP自查

@github-actions github-actions bot added Arch: RISC-V BSP related with risc-v libcpu labels Feb 22, 2025
@Rbb666
Copy link
Member

Rbb666 commented Feb 23, 2025

@heyuanjie87 这个pr请帮忙看看

@heyuanjie87
Copy link
Contributor

@heyuanjie87 这个pr请帮忙看看

我对mmu还不熟,等我查下资料

@heyuanjie87
Copy link
Contributor

GET_PPN是获取最后一级的PPN,原来代码中使用PHYSICAL_ADDRESS_WIDTH_BITS是一种错误。
pr中使用PAGE_OFFSET_BIT代替PTE_PPN_SHIFT结果正确,只是这个表达式是第二级页表的定义恰好等于了PTE的值

赞同修改,先把结果弄对

@GorrayLi
Copy link
Contributor Author

GET_PPN是获取最后一级的PPN,原来代码中使用PHYSICAL_ADDRESS_WIDTH_BITS是一种错误。 pr中使用PAGE_OFFSET_BIT代替PTE_PPN_SHIFT结果正确,只是这个表达式是第二级页表的定义恰好等于了PTE的值

赞同修改,先把结果弄对

是的,这个地方有两种计算方式,1. 根据PTE的bit位布局修改,即54-PTE_PPN_SHIFT=54-10=44;2.因为PPN最终会用在物理地址的计算上,故也可根据物理地址来计算,即PHYSICAL_ADDRESS_WIDTH_BITS-PAGE_OFFSET_BIT=56-12=44.

@GorrayLi
Copy link
Contributor Author

GET_PPN是获取最后一级的PPN,原来代码中使用PHYSICAL_ADDRESS_WIDTH_BITS是一种错误。 pr中使用PAGE_OFFSET_BIT代替PTE_PPN_SHIFT结果正确,只是这个表达式是第二级页表的定义恰好等于了PTE的值
赞同修改,先把结果弄对

是的,这个地方有两种计算方式,1. 根据PTE的bit位布局修改,即54-PTE_PPN_SHIFT=54-10=44;2.因为PPN最终会用在物理地址的计算上,故也可根据物理地址来计算,即PHYSICAL_ADDRESS_WIDTH_BITS-PAGE_OFFSET_BIT=56-12=44.

sv39

@supperthomas supperthomas merged commit 8adae07 into RT-Thread:master Feb 28, 2025
45 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Arch: RISC-V BSP related with risc-v libcpu
Projects
None yet
Development

Successfully merging this pull request may close these issues.

5 participants