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devytedevyte
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deprecate RTC_REG macros in favor of TIMER_REG macros (old typo in macro names) (#5326)
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‎tools/sdk/include/eagle_soc.h

+93-84
Original file line numberDiff line numberDiff line change
@@ -65,130 +65,139 @@
6565
#define ETS_CACHED_ADDR(addr) (addr)
6666

6767

68-
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
69-
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
70-
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
71-
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
72-
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
68+
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
69+
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
70+
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
71+
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
72+
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
7373
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) ))
7474
//}}
7575

7676
//Periheral Clock {{
77-
#define CPU_CLK_FREQ 80*1000000 //unit: Hz
78-
#define APB_CLK_FREQ CPU_CLK_FREQ
79-
#define UART_CLK_FREQ APB_CLK_FREQ
80-
#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) //divided by 256
77+
#define CPU_CLK_FREQ 80*1000000 //unit: Hz
78+
#define APB_CLK_FREQ CPU_CLK_FREQ
79+
#define UART_CLK_FREQ APB_CLK_FREQ
80+
#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) //divided by 256
8181
//}}
8282

8383
//Peripheral device base address define{{
8484
#define PERIPHS_DPORT_BASEADDR 0x3ff00000
8585
#define PERIPHS_GPIO_BASEADDR 0x60000300
8686
#define PERIPHS_TIMER_BASEDDR 0x60000600
8787
#define PERIPHS_RTC_BASEADDR 0x60000700
88-
#define PERIPHS_IO_MUX 0x60000800
88+
#define PERIPHS_IO_MUX 0x60000800
8989
//}}
9090

9191
//Interrupt remap control registers define{{
92-
#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04)
93-
#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
94-
#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
92+
#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04)
93+
#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
94+
#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
9595
//}}
9696

9797
//GPIO reg {{
98-
#define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + (reg))
99-
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + (reg), val)
100-
#define GPIO_OUT_ADDRESS 0x00
101-
#define GPIO_OUT_W1TS_ADDRESS 0x04
102-
#define GPIO_OUT_W1TC_ADDRESS 0x08
103-
104-
#define GPIO_ENABLE_ADDRESS 0x0c
105-
#define GPIO_ENABLE_W1TS_ADDRESS 0x10
106-
#define GPIO_ENABLE_W1TC_ADDRESS 0x14
107-
#define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff
108-
109-
#define GPIO_IN_ADDRESS 0x18
110-
111-
#define GPIO_STATUS_ADDRESS 0x1c
112-
#define GPIO_STATUS_W1TS_ADDRESS 0x20
113-
#define GPIO_STATUS_W1TC_ADDRESS 0x24
114-
#define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff
115-
116-
#define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c
117-
#define RTC_CALIB_START BIT31 //first write to zero, then to one to start
118-
#define RTC_PERIOD_NUM_MASK 0x3ff //max 8ms
98+
#define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + (reg))
99+
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + (reg), val)
100+
#define GPIO_OUT_ADDRESS 0x00
101+
#define GPIO_OUT_W1TS_ADDRESS 0x04
102+
#define GPIO_OUT_W1TC_ADDRESS 0x08
103+
104+
#define GPIO_ENABLE_ADDRESS 0x0c
105+
#define GPIO_ENABLE_W1TS_ADDRESS 0x10
106+
#define GPIO_ENABLE_W1TC_ADDRESS 0x14
107+
#define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff
108+
109+
#define GPIO_IN_ADDRESS 0x18
110+
111+
#define GPIO_STATUS_ADDRESS 0x1c
112+
#define GPIO_STATUS_W1TS_ADDRESS 0x20
113+
#define GPIO_STATUS_W1TC_ADDRESS 0x24
114+
#define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff
115+
116+
#define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c
117+
#define RTC_CALIB_START BIT31 //first write to zero, then to one to start
118+
#define RTC_PERIOD_NUM_MASK 0x3ff //max 8ms
119119
#define GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70
120-
#define RTC_CALIB_RDY_S 31 //after measure, flag to one, when start from zero to one, turn to zero
121-
#define RTC_CALIB_VALUE_MASK 0xfffff
120+
#define RTC_CALIB_RDY_S 31 //after measure, flag to one, when start from zero to one, turn to zero
121+
#define RTC_CALIB_VALUE_MASK 0xfffff
122122

123-
#define GPIO_PIN0_ADDRESS 0x28
123+
#define GPIO_PIN0_ADDRESS 0x28
124124

125-
#define GPIO_ID_PIN0 0
126-
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
127-
#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15)
128-
#define GPIO_ID_NONE 0xffffffff
125+
#define GPIO_ID_PIN0 0
126+
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
127+
#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15)
128+
#define GPIO_ID_NONE 0xffffffff
129129

130-
#define GPIO_PIN_COUNT 16
130+
#define GPIO_PIN_COUNT 16
131131

132-
#define GPIO_PIN_CONFIG_MSB 12
133-
#define GPIO_PIN_CONFIG_LSB 11
134-
#define GPIO_PIN_CONFIG_MASK 0x00001800
135-
#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
136-
#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
132+
#define GPIO_PIN_CONFIG_MSB 12
133+
#define GPIO_PIN_CONFIG_LSB 11
134+
#define GPIO_PIN_CONFIG_MASK 0x00001800
135+
#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
136+
#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
137137

138-
#define GPIO_WAKEUP_ENABLE 1
139-
#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE)
140-
#define GPIO_PIN_WAKEUP_ENABLE_MSB 10
141-
#define GPIO_PIN_WAKEUP_ENABLE_LSB 10
142-
#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400
143-
#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
144-
#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
138+
#define GPIO_WAKEUP_ENABLE 1
139+
#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE)
140+
#define GPIO_PIN_WAKEUP_ENABLE_MSB 10
141+
#define GPIO_PIN_WAKEUP_ENABLE_LSB 10
142+
#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400
143+
#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
144+
#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
145145

146146
#define GPIO_PIN_INT_TYPE_MASK 0x380
147-
#define GPIO_PIN_INT_TYPE_MSB 9
148-
#define GPIO_PIN_INT_TYPE_LSB 7
149-
#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
150-
#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
147+
#define GPIO_PIN_INT_TYPE_MSB 9
148+
#define GPIO_PIN_INT_TYPE_LSB 7
149+
#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
150+
#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
151151

152152
#define GPIO_PAD_DRIVER_ENABLE 1
153153
#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE)
154154
#define GPIO_PIN_PAD_DRIVER_MSB 2
155-
#define GPIO_PIN_PAD_DRIVER_LSB 2
156-
#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004
155+
#define GPIO_PIN_PAD_DRIVER_LSB 2
156+
#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004
157157
#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
158-
#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
159-
160-
#define GPIO_AS_PIN_SOURCE 0
161-
#define SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE)
162-
#define GPIO_PIN_SOURCE_MSB 0
163-
#define GPIO_PIN_SOURCE_LSB 0
164-
#define GPIO_PIN_SOURCE_MASK 0x00000001
165-
#define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB)
166-
#define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK)
158+
#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
159+
160+
#define GPIO_AS_PIN_SOURCE 0
161+
#define SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE)
162+
#define GPIO_PIN_SOURCE_MSB 0
163+
#define GPIO_PIN_SOURCE_LSB 0
164+
#define GPIO_PIN_SOURCE_MASK 0x00000001
165+
#define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB)
166+
#define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK)
167167
// }}
168168

169169
// TIMER reg {{
170-
#define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr)
171-
#define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val)
172-
#define RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask)
173-
/* Returns the current time according to the timer timer. */
174-
#define NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS)
170+
#define TIMER_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr)
171+
#define TIMER_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val)
172+
#define TIMER_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask)
173+
174+
175+
//Previous definitions of the above, kept for a while for possible compatibility, but deprecated
176+
#define RTC_REG_READ(addr) _Pragma("GCC warning \"'RTC_REG_READ' macro is deprecated\"") TIMER_REG_READ(addr)
177+
#define RTC_REG_WRITE(addr, val) _Pragma("GCC warning \"'RTC_REG_WRITE' macro is deprecated\"") TIMER_REG_WRITE(addr, val)
178+
#define RTC_CLR_REG_MASK(reg, mask) _Pragma("GCC warning \"'RTC_CLR_REG_MASK' macro is deprecated\"") TIMER_CLR_REG_MASK(reg, mask)
179+
180+
175181

176182
//load initial_value to timer1
177-
#define FRC1_LOAD_ADDRESS 0x00
183+
#define FRC1_LOAD_ADDRESS 0x00
178184

179185
//timer1's counter value(count from initial_value to 0)
180186
#define FRC1_COUNT_ADDRESS 0x04
181187

182-
#define FRC1_CTRL_ADDRESS 0x08
188+
#define FRC1_CTRL_ADDRESS 0x08
183189

184190
//clear timer1's interrupt when write this address
185-
#define FRC1_INT_ADDRESS 0x0c
186-
#define FRC1_INT_CLR_MASK 0x00000001
191+
#define FRC1_INT_ADDRESS 0x0c
192+
#define FRC1_INT_CLR_MASK 0x00000001
187193

188194
//timer2's counter value(count from initial_value to 0)
189-
#define FRC2_COUNT_ADDRESS 0x24
195+
#define FRC2_COUNT_ADDRESS 0x24
190196
// }}
191197

198+
/* Returns the current time according to the timer timer. */
199+
#define NOW() TIMER_REG_READ(FRC2_COUNT_ADDRESS)
200+
192201
//RTC reg {{
193202
#define REG_RTC_BASE PERIPHS_RTC_BASEADDR
194203

@@ -226,11 +235,11 @@
226235
#define FUNC_UART0_DTR 4
227236

228237
#define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08)
229-
#define FUNC_MTCK 0
230-
#define FUNC_I2SI_BCK 1
231-
#define FUNC_HSPID_MOSI 2
232-
#define FUNC_GPIO13 3
233-
#define FUNC_UART0_CTS 4
238+
#define FUNC_MTCK 0
239+
#define FUNC_I2SI_BCK 1
240+
#define FUNC_HSPID_MOSI 2
241+
#define FUNC_GPIO13 3
242+
#define FUNC_UART0_CTS 4
234243

235244
#define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C)
236245
#define FUNC_MTMS 0

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