expropt.conf

#------------------------------------------------------------------------
#
# ACT Synthesis Configuration File 2
#
#------------------------------------------------------------------------

begin synth 

    begin liberty

        # the liberty file used for mapping and synthesis
        # this is usually the tt corner
        string typical "${ACT_HOME}/act/syn/liberty/osu018_stdcells.lib"

        # corner setup (genus + yosys):
        
        # max power corner liberty file
        # this is usually the ff, high-temp corner
        # string max_power 

        # min delay corner liberty file
        # this is usually the ff, low-temp corner
        # string min_delay

        # max delay corner liberty file
        # this is usually the ss, high-temp corner
        # string max_delay

    end

    begin qdi

        # the matching cell libraries for converting back for QDI
        string cell_lib "${ACT_HOME}/act/syn/qdi/stdcells.act"

        # the namespace they sit in for QDI - default syn
        # string cell_lib_namespace "syn"

        # the wire type they are using for QDI - default r1of2
        # string cell_lib_wire_type "dualrail"
    end

    begin bundled

        # the matching cell libraries for converting back for BD
        string cell_lib "${ACT_HOME}/act/syn/bdopt/stdcells.act"

        # the namespace they sit in for BD - default syn
        # string cell_lib_namespace "std::cells"

        # the wire type they are using for BD - default bool
        # string cell_lib_wire_type "bool"
    end

    begin expropt

        begin cache
            # global cache location - uses this if local is unset
            # creates directory if it doesn't exist
            string global "${ACT_HOME}/cache"

            # local cache location - leave unset to use global cache
            # creates directory if it doesn't exist
            # string local "${ACT_HOME}/expr_cache"

            # cache cells namespace - will be renamed appropriately
            # when circuit is copied over from cache to expr file
            # string cell_lib_namespace "syn"

            # Erase cache - default 0
            int invalidate 0
        end

        # if synthesis files and logs are removed after being done (for debugging) - defaults to 1 (TRUE)
        int clean_tmp_files 1

        # print what is executed 0 nothing 1 dots 2 full commands - default 1
        int verbose 1

        # for speeding things up during development you can skip verification, don't use it for production chips - default 0
        # int skip_verification 0

        # define the synthesis effort 0 = low, 1 = medium, 2 = high - default 2
        # int synthesis_effort 2

        # make size-1 input/output ports arrays, instead of single bool: default 0 
        # for eg. bool in -> bool in[1] 
        # int vectorize_all_ports 0

        # set the driving cell, for STA 
        # string driving_cell LATCH

        # set the load on the output, for STA
        # real default_load 8.7

        # Logic synthesis tools report dynamic power assuming a certain clock frequency. This is the clock period.
        # Default is 100 MHz, or 10ns
        real dynamic_power_period 10e-9

        begin abc
            # use abc constraints: default 0
            int use_constraints 1
        end

        # the captable for the tech (optional) - white space to seperate files inside string
        # string captable

        # the lef file for the tech + lib  (optional) - white space to seperate files inside string
        # if the techlef is seperate it has to be the first file!
        # string lef 

        begin genus

            # search path for files
            # string searchpath

            # the sdf for genus to load (needed for genus corner analysis)
            # string timing_constraint_sdf

            # genus only qrc extraction libraries
            # string qrc_rcmin
            # string qrc_rctyp
            # string qrc_rcmax

            # genus only corner temperature used for the qrc extractiuon
            # int hightemp 125
            # typical temperature - default 25
            # int typtemp 27
            # int lowtemp -40
        end

    end

end