Simplify locking constructs #6359
Labels
Component: Core
Issue needs changes to the core
Core: HLIL
Issue involves High Level IL
Core: LLIL
Issue involves Low Level IL
Core: MLIL
Issue involves Medium Level IL
Effort: Medium
Issue should take < 1 month
Impact: Medium
Issue is impactful with a bad, or no, workaround
What is the feature you'd like to have?
The idea would be to add a (non-default) option in the settings to change the way some Load/Store operations with synchronization/lock mechanisms are lifted, to voluntarily reduce the correctness of the lifting for the sake of readability.
For instance, on arm64, the
LDX{RB,RH,R,P}
instruction family (and itsSTX{RB,RH,R,P}
counterpart) is used to make sure a sequence of LOAD and STORE is atomic, i.e. the data at the targeted address was not modified between operations. For the moment, these operations are lifted as intrinsics (see here, but the lifted code is quite cumbersome to read (and often located in a small while loops).We could implement an optional path in
il.cpp
that lifts these instructions as simple load and store operations (the latter always setting the status register to 0, indicating no synchronization problem was encountered), that could ultimately change the decompiled code of an atomic increment (for example) from:to:
Ideally, the ILs would also display a comment indicating the presence of a locking/synchronization mechanism in the original assembly; but else the user would just have to check the disassembly view themselves to make sure.
There are options already to change the way some instructions are lifted (e.g. "AARCH64 Prefer Intrinsics for Vector Operations"), so I guess this would not be technically difficult to implement.
Moreover, I think AARCH64 is not the only architecture to implement this kind of operations, the concept could be generalized to more instructions.
Thanks in advance for your consideration,
Have a great day
The text was updated successfully, but these errors were encountered: